Field-effect transistors (FETS) are typically produced using a standard complementary metal-oxide-semiconductor (CMOS) integrated circuit fabrication process. As is well known in the art, such a process allows a high degree of integration such that a high circuit density can be obtained with the use of relatively few well-established masking and processing steps. A standard CMOS process is typically used to fabricate FETs that each have a gate electrode that is composed of —type conductively doped polycrystalline silicon (polysilicon) material or other conductive materials.
The modern memory cell is composed of one transistor, such as the above described FET, and one capacitor. This modern form of the memory cell is referred to as dynamic random access memory (DRAM). In a DRAM, stored charge on the capacitor represents represent a binary one or zero while the transistor, or FET, acts as the switch interposed between the bit line or digit line and capacitor. The capacitor array plate or common node is typically charged to Vcc/2 (Vcc also written as Vdd), and therefore the charge stored on the capacitor for logic 1 is q=C*Vcc/2 and for a logic zero the stored charge is q=−C*Vcc/2 the charge is negative with respect to Vcc/2 common node voltage. The bit line or digit line connects to a multitude of transistors. The gate of the access transistor is connected to a word or row line. The wordline connects to a multitude of transistors.
In conventional DRAMS using NMOS access transistors, the transmission of a 1 or Vcc in writing a 1 into the capacitor (i.e., charging the capacitor to Vcc, though the total voltage across the capacitor is Vcc/2 as the array plate is kept at Vcc/2) is degraded unless a gate voltage higher than Vcc or Vdd is used. If the gate voltage was just kept at Vdd or Vcc the amount of voltage on the capacitor plate connected to the transistor would only be Vdd−Vtn (where Vtn is the threshold voltage). Using an n-channel access devices requires the gate voltage of the n-channel transistor be raised to Vdd+Vtn where Vtn is the threshold voltage of the NMOS transistor. This will allow the capacitor plate to see a full Vdd, e.g. [(Vdd+Vtn)−Vtn]=Vdd. Similarly for the PMOS access transistors the transmission of a zero or Vss is degraded, and the voltage of the PMOS gate has to be lowered to Vss−Vtp. The preferred voltage applied to the gate of the PMOS device when turned on in this invention is −Vtp, or more negative than Vtp. Applying this voltage to the PMOS transistor turns it on and therefore a 1 or a 0 can be written into the capacitor. If the plate connected to the PMOS is charged to Vcc or Vdd then the capacitor stores a 1, and if the plate connected to the PMOS is charged Vss then the capacitor stores a 0. Normally the array plate of the capacitor is tied to Vcc/2 and the voltage across the capacitor is Vcc/2.
The use of PMOS devices in DRAM memory cells is in itself not new, in fact the original patent (U.S. Pat. No. 3,387,286 “FIELD EFFECT TRANSISTOR MEMORY,” R. H. Dennard, 4 Jun. 1968) described both the use of NMOS and PMOS devices. In 1970, the newly formed Intel Company publicly released the 1103, the first DRAM (Dynamic Random Access Memory) chip (1K bit PMOS dynamic RAM ICs), and by 1972 it was the best selling semiconductor memory chip in the world, defeating magnetic core type memory. The first commercially available computer using the 1103 was the HP 9800 series. These devices however were based on an old technology with gate oxides in the range of 1000 angstroms, 0.1 micron, or 100 nm. PMOS devices were used because of the normally accumulated surface on n-type wafers, techniques had not yet been fully developed to control the surface inversion in the field regions of p-type wafers. With such thick gate insulators and capacitor dielectrics there was and is little consideration and concern about tunneling leakage currents.
With the development of the LOCOS process and field implantations to control surface inversion on p-type wafers the industry changed to NMOS technology and then CMOS technology on p-type wafers. Subsequent developments and scaling of devices to below 0.1 micron, or 100 nm, dimensions have resulted in the use of ultrathin gate oxides and capacitor dielectric insulators, as low as 12 angstroms, or 1.2 nm. Such ultrathin insulators can result in large tunneling currents, in the case of silicon oxide as large as 1.0 A/cm2 (S. M. Sze, “Physics of semiconductor devices,” Wiley, N.Y., 1981, pp. 402–407; T. P. Ma et al., “Tunneling leakage current in ultrathin (<4 nm) nitride/oxide stack dielectrics,” IEEE Electron Device Letters, vol. 19, no. 10, pp. 388–390, 1998). While such leakage or tunneling currents may not cause faults in microprocessors and logic circuits (R. Chau et al., “30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays,” IEEE Int. Electron, Devices Meeting, San Francisco, pp. 45–48, December 2000) they are intolerable in DRAM devices, capacitors and cells.
FIG. 1A, illustrates a conventional DRAM cell 100. As shown in FIG. 1A, the conventional DRAM cell includes a transistor 101 and a capacitor cell 102. A gate 103 for the transistor 101 is separated from the channel 104 of the transistor 100 by an insulator 106, such as an oxide. The channel region 104 of the transistor separates a source region, or first source/drain region 108 from a drain region, or second source/drain region 110. As shown in FIG. 1A, the drain region 110 is coupled to a first plate or capacitor plate 112 of the capacitor cell 102. A second plate, or array plate 114 of the capacitor cell 102 is coupled to Vdd/2. As stated above, these cells depend upon charge storage on capacitance nodes. FIG. 1A illustrates tunneling currents which are leakage currents that will discharge the cells resulting in shortened retention times and/or lost data and faults. FIG. 1A further illustrates that a cause of leakage currents is tunneling from the source/drain of the transfer device which is connected to the capacitor plate to the gate of the transistor when the transistor is off.
As illustrated in FIG. 1B, if a zero is stored in the capacitor cell 102, then the drain 110 of the transistor will be at zero or ground potential, but the gate 103 of the transistor when turned off will be a potential Vdd. This results in a large positive potential between the source/drain at ground, e.g. drain 110 and the gate 103 at potential +Vdd which can result in tunneling leakage currents. These leakage currents would tend to make the capacitor electrode more positive and can result in data errors.
Also, tunneling leakage currents from the gate 103 to substrate/channel 104 when the transistor 101 is turned on with a large negative gate 103 to source 108 voltage will result in excessive gate currents. While the tunneling current of one gate 103 may be very small, modern DRAM arrays have a large number of capacitor cells 102 and transfer devices 101. Summed over an entire array, this leakage current, which may be up to 1 A/cm2, will result in excessive power supply currents and power dissipation.
Therefore, there is a need in the art to provide improved techniques for controlling tunneling currents in DRAM capacitors, cells and devices. Such improved techniques should take into power supply currents and power dissipation issues.